Although it can in principle be applied to any desired integrated circuits, the present invention and the problem on which it is based are explained in connection with integrated memory circuits, in particular DRAM cells, produced using silicon technology.
It is known that a stacked capacitor is preferably connected at the bottom to a transistor in order to form a DRAM cell. During the known fabrication of stacked capacitors, in particular of cylindrical stacked capacitors in a stacked capacitor array, the problem arises of the mechanical stability of the individual stacked capacitors decreasing as their aspect ratio increases. If the aspect ratio of capacitors in column or crown form rises above a certain value, the structures become mechanically unstable. The capacitors may disadvantageously adopt an inclination toward one another as a result of this instability. If two adjacent capacitors are inclined toward one another to such an extent that they come into contact with one another, a short circuit is produced between these two capacitors. Memory errors occur within a stacked capacitor array as a result of a short circuit between two capacitors.
Hitherto, this problem has been solved by keeping the aspect ratio of the individual capacitors below an empirically determined limit value. However, this limits the capacitance which can be achieved per capacitor.
However, to further improve the large scale integration of memory circuits, it is necessary to increase the capacitance of the respective capacitor per unit chip surface area by increasing the aspect ratio.